This invention relates to a semiconductor memory device and, more particularly, to a technique effectively applied to a semiconductor memory having a memory cell constituted by a series circuit of a capacitor element and a MISFET.
A memory cell of a dynamic random access memory (DRAM) is constituted by a series circuit of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a capacitor element. To increase the degree of integration of DRAMs, techniques for reducing the area which is occupied by the capacitor element, without decreasing the capacitance value thereof, have heretofore been studied. Examples of such techniques include one in which a surface portion of a semiconductor substrate near a MISFET is etched in the depthwise direction to form a trench or moat, and a capacitor element is formed using this moat. In such a case, a first electrically conductive layer for providing the capacitor element may be connected to one of the semiconductor regions of the MISFET. In this case, a contact hole for connecting the first electrically conductive layer and this semiconductor region needs to be formed in the upper surface of the semiconductor region, and this increases the area required for the memory cell.
To overcome the above-described problem, one technique has already been mentioned in "Nikkei Electronics", Jan. 14, 1985, pp. 122-123, published by Nikkei McGraw-Hill, in which a moat is formed around a MISFET provided in a semiconductor substrate, and a contact hole is formed in a predetermined portion of the inner wall of this moat, and the electrically conductive layer of the capacitor element is connected with one of the semiconductor regions of the MISFET through the contact hole. This technique is also described in the Technical Digest of the 1984 International Electron Devices Meeting, pp. 240-243.